By Richard Munden
Richard Munden demonstrates tips on how to create and use simulation types for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf electronic elements. in line with the VHDL/VITAL general, those versions contain timing constraints and propagation delays which are required for exact verification of ultra-modern electronic designs. ASIC and FPGA Verification: A consultant to part Modeling expertly illustrates how ASICs and FPGAs may be confirmed within the better context of a board or a procedure. it's a worthy source for any fashion designer who simulates multi-chip electronic designs. *Provides a variety of versions and a in actual fact outlined method for appearing board-level simulation.*Covers the main points of modeling for verification of either good judgment and timing. *First ebook to assemble and educate strategies for utilizing VHDL to version "off-the-shelf" or "IP" electronic parts to be used in FPGA and board-level layout verification.
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Extra resources for ASIC and FPGA Verification : A Guide to Component Modeling (The Morgan Kaufmann Series in Systems on Silicon)
They are discussed in Chapters 3 and 6. 5 Interconnect Delays Although the model is now much improved, there is still something missing. At the board level, components are connected by copper printed circuit board traces. Depending on their lengths and the design’s timing requirements, the delays introduced by these traces can be significant. Therefore, they need to be accounted for in the models. Many PCB design tools and signal integrity analysis tools are capable of determining interconnect delays.
1 Declarations The VITAL_Timing package declares many types that we will use extensively. Here are the ones with which you will become most familiar: VitalDelayType is a subtype of TIME. It is used to hold simple delays. VitalDelayType01 is an array of TIME. It holds two values for rising (tr01) and falling (tr10) transition delays. It is used to hold delays for 2-state outputs. VitalDelayType01Z is an array of TIME. It holds six values for tr01, tr10, tr0Z, trZ1, tr1Z, and trZ0 transitions, in that order.
There is at least one other case when an output is given an initial value other than ‘U’. Some ECL logic parts have a VBB output. These pins are initialized to ‘W’ for reasons discussed in Chapter 16. 2 we have a model that would function correctly as a nand gate but has zero delay. All physical parts have some delay. Sometimes we rely on that delay, other times we would like it to go away, but we always have to account for it. So how do we add delays to our models? The simplest way of expressing a delay in VHDL is with an AFTER clause: YNeg <= A nand B AFTER 6 ns; This is fine if the part you are modeling happens to switch in 6 nanoseconds, in both directions, under all conditions.
ASIC and FPGA Verification : A Guide to Component Modeling (The Morgan Kaufmann Series in Systems on Silicon) by Richard Munden